Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
INTEGRATION TOOLS
78
Name Pin
Description
Specification
Requirement
Notes
RESET#
1
Reset signal from MP
cluster to ITP.
Terminate
2
signal properly at
the debug port.
Debug port must be at the end
of the signal trace.
Connected to high-speed
comparator (biased at 2/3 of the
level found at the POWERON pin)
on the ITP buffer board. Additional
load does not change timing
calculations for the processor bus
agents if routed properly.
DBRESET#
3
Allows ITP to reset entire
target system.
Tie signal to target system
reset (recommendation):
PWR_OK signal on PCIset as
an ORed input).
Pulled-up signal with the proper
resistor (see Signal Notes
section, following).
Open drain output from ITP to the
target system. It will be held
asserted for 100 ms; capacitance
needs to be small enough to
recognize assert. The pull-up
resistor should be picked to (1)
meet VIL of target system and (2)
meet specified rise time.
TCK
5
The TAP (Test Access
Port) clock from ITP to MP
cluster.
Add 1.0K
Ω pull-up resistor to
Vcc_
TAP
near driver.
For MP systems, each
processor should receive a
separately buffered TCK.
Add a series termination
resistor or a Bessel filter on
each output.
Poor routing can cause multiple
clocking problems. Should be
routed to all components in the
boundary scan chain
3
.
Simulations should be run to
determine the proper value for
series termination or Bessel filter,
see figure 31.
TMS
7
Test mode select signal
from ITP to MP cluster,
controls the TAP finite
state machine.
Add 1.0 K
Ω pull-up resistor to
Vcc_
TAP
near driver.
For MP systems, each
processor should receive a
separately buffered TMS.
Add a series termination
resistor on each output.
Operates synchronously with TCK.
Should be routed to all components
in the boundary scan chain
3
.
Simulations should be run to
determine the proper value for
series termination.
TDI
8
Test data input signal from
ITP to first component in
boundary scan chain of
MP cluster; inputs test
instructions and data
serially.
This signal is open-drain from
the ITP. However, TDI is pulled
up to Vcc_
TAP
with ~150
Ω on
the processor. Add a 150 to
330
Ω pull-up resistor (to
Vcc_
TAP
) if TDI will not be
connected directly to a
processor.
Operates synchronously with TCK.
POWERON
9
Used by ITP to determine
when target system power
is ON and, once target
system is ON, enables all
debug port electrical
interface activity. From
target V
TT
to ITP.
Add 1.5K
Ω pull-up resistor (to
V
TT
).
If no power is applied, the ITP will
not drive any signals; isolation
provided using isolation gates.
Voltage applied is internally used to
set AGTL+ threshold (or reference)
at 2/3 V
TT
.
TDO
10
Test data output signal
from last component in
from last component in
boundary scan chain of
MP cluster to ITP; test
output is read serially.
Add 150
Ω pull-up resistor (to
Vcc_
TAP
).
Design pull-ups to route around
empty processor sockets (so
resistors are not in parallel).
Operates synchronously with TCK.
Each processor has a 25
Ω driver.
DBINST#
11
Indicates to target system
that the ITP is installed.
Add ~10K
Ω pull-up resistor.
Not required if boundary scan is not
used in target system.
TRST#
12
Test reset signal from ITP
to MP cluster, used to
reset TAP logic.
Add ~680
Ω pull-down.
To disable TAP reset if ITP not
installed.
Asynchronous input signal.