Intel i7-3920XM Extreme AW8063801009607 User Manual

Datasheet, Volume 2

51

Processor Configuration Registers 

14

RW1C

0b

Uncore

Signaled System Error (SSE) 
This bit is set to 1 when Device 0 generates an SERR message 

over DMI for any enabled Device 0 error condition. Device 0 error 

conditions are enabled in the PCICMD, ERRCMD, and DMIUEMSK 

registers. Device 0 error flags are read/reset from the PCISTS, 

ERRSTS, or DMIUEST registers. Software clears this bit by writing 

a 1 to it.

13

RW1C

0b

Uncore

Received Master Abort Status (RMAS) 
This bit is set when the processor generates a DMI request that 

receives an Unsupported Request completion packet. Software 

clears this bit by writing a 1 to it.

12

RW1C

0b

Uncore

Received Target Abort Status (RTAS) 
This bit is set when the processor generates a DMI request that 

receives a Completer Abort completion packet. Software clears 

this bit by writing a 1 to it.

11

RO

0b

Uncore

Signaled Target Abort Status (STAS) 
The processor will not generate a Target Abort DMI completion 

packet or Special Cycle. This bit is not implemented and is 

hardwired to a 0. Writes to this bit position have no effect.

10:9

RO

00b

Uncore

DEVSEL Timing (DEVT) 
These bits are hardwired to 00. Writes to these bit positions have 

no effect. Device 0 does not physically connect to PCI_A. These 

bits are set to 00 (fast decode) so that optimum DEVSEL timing 

for PCI_A is not limited by the Host.

8

RW1C

0b

Uncore

Master Data Parity Error Detected (DPD) 
This bit is set when DMI received a Poisoned completion from PCH.
This bit can only be set when the Parity Error Enable bit in the PCI 

Command register is set.

7

RO

1b

Uncore

Fast Back-to-Back (FB2B) 
This bit is hardwired to 1. Writes to these bit positions have no 

effect. Device 0 does not physically connect to PCI_A. This bit is 

set to 1 (indicating fast back-to-back capability) so that the 

optimum setting for PCI_A is not limited by the Host.

6

RO

0h

5

RO

0b

Uncore

66 MHz Capable (MC66) 
Does not apply to PCI Express. Must be hardwired to 0.

4

RO

1b

Uncore

Capability List (CLIST) 
This bit is hardwired to 1 to indicate to the configuration software 

that this device/function implements a list of new capabilities. A 

list of new capabilities is accessed using register CAPPTR at 

configuration address offset 34h. Register CAPPTR contains an 

offset pointing to the start address within configuration space of 

this device where the Capability Identification register resides.

3:0

RO

0h