Intel 1005M AW8063801121200 User Manual
Product codes
AW8063801121200
Electrical Specifications
102
Datasheet, Volume 1
7.7
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.6-
2003 standards. Some small portion of the I/O pins may support only one of these
standards.
2003 standards. Some small portion of the I/O pins may support only one of these
standards.
7.8
Component Storage Condition Specifications
(Prior to Board Attach)
This section applies to component level storage prior to board attach. Environmental
storage condition limits define the temperature and relative humidity to which the
device is exposed to while being stored in applicable Intel shipping media trays, reels,
moisture barrier bags and Boxes, and the component is not electrically connected.
storage condition limits define the temperature and relative humidity to which the
device is exposed to while being stored in applicable Intel shipping media trays, reels,
moisture barrier bags and Boxes, and the component is not electrically connected.
Post board attach storage conditions and limits are not specified for non-intel branded
boards.
boards.
specifies absolute maximum and minimum storage temperature and humidity
limits for given time durations. Failure to adhere to the specified limits could result in
physical damage to the component. If this is suspected, Intel recommends a visual
inspection to determine possible physical damage to the silicon or surface components.
physical damage to the component. If this is suspected, Intel recommends a visual
inspection to determine possible physical damage to the silicon or surface components.
Notes:
1.
Specified temperatures are not to exceed values based on data collected. Exceptions for surface mount
reflow are specified by the applicable JEDEC standard. Non-adherence may affect processor reliability.
2.
Component product device storage temperature qualification methods may follow JESD22-A119 (low temp)
and JESD22-A103 (high temp) standards when applicable for volatile memory.
3.
Component stress testing is conducted in conformance with JESD22-A104.
4.
The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisture
sensitive devices removed from the moisture barrier bag.
Table 7-4.
Storage Condition Ratings
Symbol
Parameter
Min
Max
Notes
T
absolute storage
Device storage temperature when exceeded for any
length of time
-25
°C
125
°C
1, 2, 3, 4
T
short term storage
The ambient storage temperature and time for up to
72 hours.
-25
°C
85
°C
1, 2, 3, 4
T
sustained storage Time
and Temp
The ambient storage temperature and time for up to
30 months.
-5
°C
40
°C
1, 2, 3, 4
RH
sustained storage
The maximum device storage relative humidity for up
to 30 months.
60% @ 24
°C
1, 2, 3, 4