Intel 1005M AW8063801121200 User Manual

Datasheet, Volume 1

111

The PECI interface operates at a nominal voltage set by V

CCIO

 The set of DC electrical 

specifications shown in 

 is used with devices normally operating from a V

CCIO

 

interface supply. V

CCIO 

nominal levels will vary between processor families. All PECI 

devices will operate at the V

CCIO

 level determined by the processor installed in the 

system. For specific nominal V

CCIO

 levels, refer to 

1.

V

CCIO 

supplies the PECI interface. PECI behavior does not affect V

CCIO

 Min / Max specifications.

2.

The leakage specification applies to powered devices on the PECI bus.

3.

The PECI buffer internal pull-up resistance measured at 0.75*V

CCIO

The input buffers in both client and host models must use a Schmitt-triggered input 
design for improved noise immunity. Use 

 as a guide for input buffer design.

R

up

Output resistance

15

45



3

V

in

Input Voltage Range

-0.15

V

CCIO

V

V

hysteresis

Hysteresis

0.1 * V

CCIO

N/A

V

V

n

Negative-Edge Threshold Voltage

0.275 * V

CCIO

0.500 * V

CCIO

V

V

p

Positive-Edge Threshold Voltage

0.550 * V

CCIO

0.725 * V

CCIO

V

C

bus

Bus Capacitance per Node

N/A

10

pF

Cpad

Pad Capacitance

0.7

1.8

pF

Ileak000

leakage current @ 0V

—

0.6

mA

Ileak025

leakage current @ 0.25*V

CCIO

—

0.4

mA

Ileak050

leakage current @ 0.50*V

CCIO

—

0.2

mA

Ileak075

leakage current @ 0.75*V

CCIO

—

0.13

mA

Ileak100

leakage current @ V

CCIO

—

0.10

mA