Intel 1005M AW8063801121200 User Manual

Product codes

AW8063801121200

Datasheet, Volume 1

Introduction

1.2.6

Embedded DisplayPort* (eDP*)

• Stand alone dedicated port (unlike two generations ago that shared pins with PCIe

interface)

1.2.7

Intel

Flexible Display Interface (Intel

FDI)

• For SKUs with graphics, carries display traffic from the Processor Graphics in the

processor to the legacy display connectors in the PCH

• Based on DisplayPort standard
• The two Intel FDI links are capable of being configured to support three

independent channels, one for each display pipeline

• There are two Intel FDI channels, each one consists of four unidirectional

downstream differential transmitter pairs:

— Scalable down to 3X, 2X, or 1X based on actual display bandwidth

requirements

— Fixed frequency 2.7 GT/s data rate

• Two sideband signals for display synchronization:

— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)

• One Interrupt signal used for various interrupts from the PCH:

— FDI_INT signal shared by both Intel FDI Links

• PCH supports end-to-end lane reversal across both links
• Common 100-MHz reference clock

1.3

Power Management Support

1.3.1

Processor Core

• Full support of ACPI C-states as implemented by the following processor C-states:

— C0, C1, C1E, C3, C6, C7

• Enhanced Intel SpeedStep Technology

1.3.2

System

• S0, S3, S4, S5

1.3.3

Memory Controller

• Conditional self-refresh (Intel

Rapid Memory Power Management (Intel

RMPM))

• Dynamic power down

1.3.4

PCI Express*

• L0s and L1 ASPM power management capability

1.3.5

Direct Media Interface (DMI)

• L0s and L1 ASPM power management capability