Intel 1005M AW8063801121200 User Manual
Product codes
AW8063801121200
Datasheet, Volume 1
25
Interfaces
2
Interfaces
This chapter describes the interfaces supported by the processor.
2.1
System Memory Interface
2.1.1
System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 / DDR3L / DDR3L-RS protocols
with two independent, 64-bit wide channels, each accessing one or two DIMMs. The
IMC supports one or two, unbuffered non-ECC DDR3 DIMM per-channel; thus, allowing
up to four device ranks per-channel.
with two independent, 64-bit wide channels, each accessing one or two DIMMs. The
IMC supports one or two, unbuffered non-ECC DDR3 DIMM per-channel; thus, allowing
up to four device ranks per-channel.
Note:
The processor supports only JEDEC approved memory modules and devices.
Note:
2 DIMMs per channel supported only in Quad-Core rPGA package.
• DDR3 / DDR3L / DDR3L-RS
at 1.5
V Data Transfer Rates
— 1333 MT/s (PC3-10600), 1600 MT/s (PC3-12800)
• DDR3L / DDR3L-RS at 1.35
V Data Transfer Rates
— 1333 MT/s (PC3-10600), 1600 MT/s (PC3-12800)
• DDR3 / DDR3L / DDR3L-RS DRAM Device Technology
— Standard 1-Gb, 2-Gb, and 4-Gb technologies and addressing are supported for
x16 and x8 devices. There is no support for memory modules with different
technologies or capacities on opposite sides of the same memory module. If
one side of a memory module is populated, the other side is either identical or
empty.
Table 2-1.
Processor Mobile DIMM Support Summary by Product
Processor Cores
Package
DIMM per Channel
DDR3 / DDR3L /
DDR3L-RS
at 1.5 V
DDR3L /
DDR3L-RS
at 1.35
V
Dual Core,
Quad Core
Quad Core
rPGA, BGA
1 DPC
1333/1600
1333/1600
Quad Core
rPGA
2 DPC
1333/1600
1333