Intel 1005M AW8063801121200 User Manual

Datasheet, Volume 1

39

The display pipe blends and synchronizes pixel data received from one or more display 
planes and adds the timing of the display output device upon which the image is 
displayed.

The display pipes A, B, and C operate independently of each other at the rate of 1 pixel 
per clock. They can attach to any of the display ports. Each pipe sends display data to 
eDP or to the PCH over the Intel Flexible Display Interface (Intel FDI).

The display ports consist of output logic and pins that transmit the display data to the 
associated encoding logic and send the data to the display device (that is, LVDS, 
HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are 
now repartitioned and driven from the PCH with the exception of the eDP DisplayPort. 
Refer to the PCH datasheet for more details on display port support.

The Processor Graphics supports the Embedded Display Port (eDP) interface, intended 
for display devices that are integrated into the system (such as laptop LCD panel). 
DisplayPort consolidates internal and external connection methods to reduce device 
complexity, support cross industry applications, and provide performance scalability. 
The eDP interface supports link-speeds of 1.62

 

Gbps and 2.7 Gbps on 1, 2, or 4 data 

lanes. The eDP supports -0.5% SSC and non-SSC clock settings.

The eDP on the processor is compliant with VESA DP specification 1.1a, except the 
electrical parameters that appear in 

. The eDP interface supports Alternate Scrambler Seed Reset (ASSR) for 

eDP display authentication; thereby, enabling secure transfer of protected content over 
the cable to sink device.

The Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying display 
traffic from the Processor Graphics controller to the PCH display I/Os. Intel FDI 
supports two or three independent channels – one for pipe A, one for pipe B, and one 
for Pipe C.

Channels A and B have a maximum of four transmit (Tx) differential pairs used for 
transporting pixel and framing data from the display engine in two display 
configurations. In three display configurations Channel A has 4 transmit (Tx) 
differential pairs while Channel B and C have two transmit (Tx) differential pairs.

• Each channel has four transmit (Tx) differential pairs used for transporting pixel 

and framing data from the display engine

• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS 

signaling)

• One display interrupt line input (1-V CMOS signaling)
• Intel FDI may dynamically scale down to 2X or 1X based on actual display 

bandwidth requirements

• Common 100-MHz reference clock
• Each channel transports at a rate of 2.7 Gbps
• PCH supports end-to-end lane reversal across both channels (no reversal support 

required in the processor)