Intel 1005M AW8063801121200 User Manual
Product codes
AW8063801121200
Power Management
58
Datasheet, Volume 1
4.2.4.5
Core C7 State
Note:
The terms “Core C6 state” and “Core C7 state” defines the same
individual core
power
state. In both cases the processor cores that request either C6 or C7 will enter the C6
state.
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to
the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same
behavior as the core C6 state unless the core is the last one in the package to enter the
C7 state. If it is, that core is responsible for flushing L3 cache ways. The processor
supports the C7s substate. When an MWAIT(C7) command is issued with a C7s
sub-state hint, the entire L3 cache is flushed one step as opposed to flushing the L3
cache in multiple steps.
the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same
behavior as the core C6 state unless the core is the last one in the package to enter the
C7 state. If it is, that core is responsible for flushing L3 cache ways. The processor
supports the C7s substate. When an MWAIT(C7) command is issued with a C7s
sub-state hint, the entire L3 cache is flushed one step as opposed to flushing the L3
cache in multiple steps.
4.2.4.6
C-State Auto-Demotion
In general, deeper C-states such as C6 or C7 have long latencies and have higher
energy entry / exit costs. The resulting performance and energy penalties become
significant when the entry / exit frequency of a deeper C-state is high. Therefore,
incorrect or inefficient usage of deeper C-states have a negative impact on battery life.
To increase residency and improve battery life in deeper C-states, the processor
supports C-state auto-demotion.
energy entry / exit costs. The resulting performance and energy penalties become
significant when the entry / exit frequency of a deeper C-state is high. Therefore,
incorrect or inefficient usage of deeper C-states have a negative impact on battery life.
To increase residency and improve battery life in deeper C-states, the processor
supports C-state auto-demotion.
There are two C-State auto-demotion options:
• C7/C6 to C3
• C7/C6/C3 To C1
• C7/C6/C3 To C1
The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 is based on each
core’s immediate residency history. Upon each core C6/C7 request, the core C-state is
demoted to C3 or C1 until a sufficient amount of residency has been established. At
that point, a core is allowed to go into C3/C6 or C7. Each option can be run
concurrently or individually.
core’s immediate residency history. Upon each core C6/C7 request, the core C-state is
demoted to C3 or C1 until a sufficient amount of residency has been established. At
that point, a core is allowed to go into C3/C6 or C7. Each option can be run
concurrently or individually.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
4.2.5
Package C-States
The processor supports C0, C1/C1E, C3, C6, and C7 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package C-
states unless specified otherwise:
summary of the general rules for package C-state entry. These apply to all package C-
states unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
— For package C-states, the processor is not required to enter C0 before entering
any other C-state.