Intel 1005M AW8063801121200 User Manual

Product codes
AW8063801121200
Page of 172
Power Management 
64
Datasheet, Volume 1
The target behavior is to enter self-refresh for the package C3, C6, and C7 states as 
long as there are no memory requests to service.
4.3.2.3
Dynamic Power Down Operation
Dynamic power down of memory is employed during normal operation. Based on idle 
conditions, a given memory rank may be powered down. The IMC implements 
aggressive CKE control to dynamically put the DRAM devices in a power down state. 
The processor core controller can be configured to put the devices in active power down 
(CKE de-assertion with open pages) or precharge power down (CKE de-assertion with 
all pages closed). Precharge power down provides greater power savings but has a 
bigger performance impact, since all pages will first be closed before putting the 
devices in power down mode.
If dynamic power down is enabled, all ranks are powered up before doing a refresh 
cycle and all ranks are powered down at the end of refresh.
4.3.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic 
interference. This includes all signals associated with an unused memory channel. 
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-
DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the 
input receiver (differential sense-amp) should be disabled, and any DLL circuitry 
related ONLY to unused signals should be disabled. The input path must be gated to 
prevent spurious results due to noise on the unused signals (typically handled 
automatically when input receiver is disabled).
4.3.3
DDR Electrical Power Gating (EPG)
The DDR I/O of the processor supports on-die Electrical Power Gating (DDR-EPG) 
during normal operation (S0 mode) while the processor is at package C3 or deeper 
power state.
During EPG, the V
CCIO
 internal voltage rail will be powered down, while V
DDQ
 and the 
un-gated V
CCIO
 will stay powered on.
The processor will transition in and out of DDR EPG mode on an as needed basis 
without any external pins or signals.
Table 4-12. Targeted Memory State Conditions
Mode
Memory State with Processor Graphics
Memory State with External Graphics
C0, C1, C1E
Dynamic memory rank power down based on 
idle conditions.
Dynamic memory rank power down based on 
idle conditions.
C3, C6, C7
If the processor graphics engine is idle and 
there are no pending display requests, then 
enter self-refresh. Otherwise use dynamic 
memory rank power down based on idle 
conditions.
If there are no memory requests, then enter 
self-refresh. Otherwise use dynamic memory 
rank power down based on idle conditions.
S3
Self-Refresh Mode.
Self-Refresh Mode.
S4
Memory power down (contents lost).
Memory power down (contents lost)