Intel 1005M AW8063801121200 User Manual

Datasheet, Volume 1

85

This chapter describes the processor signals. They are arranged in functional groups 
according to their associated interface or category. The following notations are used to 
describe the signal type. 

The signal description also includes the type of buffer used for the particular signal 
(see

 

1.

Qualifier for a buffer type.

I

Input Signal

O

Output Signal

I/O

Bi-directional Input/Output Signal

PCI Express*

PCI Express* interface signals. These signals are compatible with PCI Express* 3.0 

Signalling Environment AC Specifications and are AC coupled. The buffers are not  

3.3-V tolerant. Refer to the PCIe specification.

eDP

Embedded Display Port interface signals. These signals are compatible with VESA 

Revision 1.1a DP specifications and the interface is AC coupled. The buffers are not 

3.3-V tolerant.

Intel FDI

Intel Flexible Display interface signals. These signals are based on PCI Express* 2.0 

Signaling Environment AC Specifications (2.7 GT/s), but are DC coupled. The buffers 

are not 3.3-V tolerant.

DMI

Direct Media Interface signals. These signals are compatible with PCI Express* 2.0 

Signaling Environment AC Specifications, but are DC coupled. The buffers are not  

3.3-V tolerant.

CMOS

CMOS buffers. 

DDR3

DDR3 buffers: 1.5-V tolerant

DDR3L

DDR3L buffers: 1.35-V tolerant. 

A

Analog reference or output. May be used as a threshold voltage or for buffer 

compensation

Ref

Voltage reference signal

Asynchronous

1

Signal has no timing relationship with any reference clock.