Intel J1750 FH8065301562600 User Manual
Product codes
FH8065301562600
PCU – iLB – Interrupt Decoding and Routing
1246
Datasheet
29.1.2.1
Routing PCI Based Interrupts to 8259 PIC
The interrupt router can be programmed to allow PIRQA-PIRQH to be routed internally
to the 8259 as ISA compatible interrupts IRQ 3–7, 9–12 & 14–15. The assignment is
programmable through the 8 PIRQx Routing Control Registers: PIRQA, PIQRB, PIRQC,
PIRQD, PIRQE, PIRQF, PIRQG, PIRQH. One or more PIRQs can be routed to the same
IRQ input. If ISA Compatible Interrupts are not required, the Route registers can be
programmed to disable steering.
to the 8259 as ISA compatible interrupts IRQ 3–7, 9–12 & 14–15. The assignment is
programmable through the 8 PIRQx Routing Control Registers: PIRQA, PIQRB, PIRQC,
PIRQD, PIRQE, PIRQF, PIRQG, PIRQH. One or more PIRQs can be routed to the same
IRQ input. If ISA Compatible Interrupts are not required, the Route registers can be
programmed to disable steering.
The PIRQx# lines are defined as active low, level sensitive. When a PIRQx# is routed to
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
sensitive mode. The processor internally inverts the PIRQx# line to send an active high
level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no
longer be used by an active high device (through SERIRQ). However, active low
interrupts can share their interrupt with PCI interrupts.
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
sensitive mode. The processor internally inverts the PIRQx# line to send an active high
level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no
longer be used by an active high device (through SERIRQ). However, active low
interrupts can share their interrupt with PCI interrupts.
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