Analog Devices AD8072 Evaluation Board AD8072ARM-EBZ AD8072ARM-EBZ Data Sheet

 

 

 

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The Analog Devices, Inc., high speed universal evaluation 
board (EB-O8RM-2Z) is designed to help customers quickly 
prototype new dual op amp circuits and reduce design time. 
The evaluation board can be used with almost any Analog 
Devices dual op amp in various configurations and applications. 
Figure 1 shows the component side of the bare evaluation board, 
and Figure 2 shows the circuit side of the bare evaluation board.  

The evaluation board is a 2-layer PCB that accepts SMA con-
nectors on the input and output for efficient connection to test 
equipment. The ground plane, component placement, and supply 
bypassing are laid out to minimize parasitic inductances and 
capacitances. The evaluation board components are primarily 
SMT 0805 case size, with the exception of the electrolytic  
bypass capacitors (C1, C2), which are 3528 case size. 

There are two options for supply bypassing. The first option is 
connecting additional shunt capacitors (C3, C4) in parallel with 
the electrolytic capacitors (C1, C2) from each supply to ground. 
This technique of power supply bypassing provides wideband 
rejection of unwanted noise on the supply lines. It is implemented 
by placing a 0 Ω resistor in the C5 position and shunt capacitors 
in the C1, C2, C3, and C4 positions. 

The second approach to supply bypassing is to connect one 
capacitor between the supply rails. This method uses fewer 
components and can improve the power supply rejection ratio 
(PSRR) at higher frequencies. It is implemented by inserting a 0 Ω 
resistor in the C3 position, inserting the bypass capacitor in the C4 
position, and omitting C5. Optimal bypassing is circuit dependent 
and therefore must be evaluated by the designer. 

Figure 3 shows the evaluation board schematic. Figure 4 and 
Figure 6 show the evaluation board assembly drawings. The 
PCB layout pattern for the component side is shown in Figure 5, 
and the PCB layout pattern for the circuit side is shown in 
Figure 7.  

 

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