Atmel Evaluation Kit AT91SAM9260-EK AT91SAM9260-EK Data Sheet

Product codes
AT91SAM9260-EK
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SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
 
7.
Processor and Architecture
7.1
ARM926EJ-S Processor
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RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
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Two Instruction Sets
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ARM High-performance 32-bit Instruction Set
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Thumb High Code Density 16-bit Instruction Set
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DSP Instruction Extensions
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5-Stage Pipeline Architecture:
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Instruction Fetch (F)
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Instruction
 
Decode (D)
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Execute (E)
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Data Memory (M)
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Register Write (W)
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8-Kbyte Data Cache, 8-Kbyte Instruction Cache
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Virtually-addressed 4-way Associative Cache
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Eight words per line
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Write-through and Write-back Operation
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Pseudo-random or Round-robin Replacement
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Write Buffer
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Main Write Buffer with 16-word Data Buffer and 4-address Buffer
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DCache Write-back Buffer with 8-word Entries and a Single Address Entry
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Software Control Drain
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Standard ARM v4 and v5 Memory Management Unit (MMU)
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Access Permission for Sections
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Access Permission for large pages and small pages can be specified separately for each quarter of the 
page 
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16 embedded domains
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Bus Interface Unit (BIU)
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Arbitrates and Schedules AHB Requests
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Separate Masters for both instruction and data access providing complete Matrix system flexibility
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Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
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On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
7.2
Bus Matrix
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6-layer Matrix, handling requests from 6 masters
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Programmable Arbitration strategy
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Fixed-priority Arbitration
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Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
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Burst Management 
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Breaking with Slot Cycle Limit Support
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Undefined Burst Length Support
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One Address Decoder provided per Master
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Three different slaves may be assigned to each decoded memory area: one for internal boot, one for 
external boot, one after remap