Atmel Evaluation Kit AT91SAM9260-EK AT91SAM9260-EK Data Sheet
Product codes
AT91SAM9260-EK
20
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High
Performance Bus (AHB) for its Master and Slave interfaces with additional features.
Performance Bus (AHB) for its Master and Slave interfaces with additional features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI
that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing
of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved
for the peripherals and provides access to the Advanced Peripheral Bus (APB).
that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing
of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved
for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master requesting such an
access.
access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in
order to simplify the mappings, all the masters have a similar address decoding.
order to simplify the mappings, all the masters have a similar address decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory
space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to
space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to
for details.
A complete memory map is presented in
8.1
Embedded Memories
z
32 KB ROM
z
Single Cycle Access at full matrix speed
z
Two 4 KB Fast SRAM
z
Single Cycle Access at full matrix speed
8.1.1
Boot Strategies
summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS
state at reset.
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can
be configured with two parameters.
be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software
once the system has booted. Refer to the Bus Matrix Section for more details.
once the system has booted. Refer to the Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is
done via hardware at reset.
Note:
done via hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in
complete memory map presented in
.
The SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory
area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose.
area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.
8.1.1.1 BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
z
Boot on slow clock (On-chip RC or 32,768 Hz)
z
Auto baudrate detection
Table 8-1.
Internal Memory Mapping
Address
REMAP = 0
REMAP = 1
BMS = 1
BMS = 0
0x0000 0000
ROM
EBI_NCS0
SRAM0 4K