Atmel Xplained Evaluation Kit ATMEGA1284P-XPLD ATMEGA1284P-XPLD Data Sheet
Product codes
ATMEGA1284P-XPLD
8
8272ES–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the Atmel
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on
page 85
.
2.3.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
P o r t D a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on
page 88
.
2.3.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in
reset, even if the clock is not running. The minimum pulse length is given in
”” on page 337
.
Shorter pulses are not guaranteed to generate a reset.
2.3.8
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.9
XTAL2
Output from the inverting Oscillator amplifier.
2.3.10
AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be exter-
nally connected to V
nally connected to V
CC
, even if the ADC is not used. If the ADC is used, it should be connected
to V
CC
through a low-pass filter.
2.3.11
AREF
This is the analog reference pin for the Analog-to-digital Converter.