Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet
Product codes
AT32UC3L0-XPLD
63
32099G–06/2011
AT32UC3L016/32/64
7.10
Timing Characteristics
7.10.1
Startup, Reset, and Wake-up Timing
The startup, reset, and wake-up timings are calculated using the following formula:
Where
and
are found in
.
is the period of the CPU clock. If
another clock source than RCSYS is selected as CPU clock the startup time of the oscillator,
, must added to the wake-up time in the stop, deepstop, and static sleep modes.
Please refer to the source for the CPU clock in the
for
more details about oscillator startup times.
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
7.10.2
RESET_N Timing
Note:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
t
t
CONST
N
CPU
t
CPU
×
+
=
t
CONST
N
CPU
t
CPU
t
OSCSTART
Table 7-36.
Maximum Reset and Wake-up Timing
Parameter
Measuring
Max (in
µs)
Max
Startup time from power-up, using
regulator
regulator
Time from VDDIN crossing the V
POT+
threshold of
POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is supplied by the internal
regulator.
stage of CPU. VDDCORE is supplied by the internal
regulator.
2210
0
Startup time from power-up, no
regulator
regulator
Time from VDDIN crossing the V
POT+
threshold of
POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is connected to VDDIN.
stage of CPU. VDDCORE is connected to VDDIN.
1810
0
Startup time from reset release
Time from releasing a reset source (except POR18,
POR33, and SM33) to the first instruction entering
the decode stage of CPU.
POR33, and SM33) to the first instruction entering
the decode stage of CPU.
170
0
Wake-up
Idle
From wake-up event to the first instruction of an
interrupt routine entering the decode stage of the
CPU.
interrupt routine entering the decode stage of the
CPU.
0
19
Frozen
0
110
Standby
0
110
Stop
27 +
116
Deepstop
27 +
116
Static
97 +
116
Wake-up from shutdown
From wake-up event to the first instruction entering
the decode stage of the CPU.
the decode stage of the CPU.
1180
0
t
CONST
N
CPU
t
OSCSTART
t
OSCSTART
t
OSCSTART
Table 7-37.
RESET_N Waveform Parameters
Symbol
Parameter
Conditions
Min
Max
Units
t
RESET
RESET_N minimum pulse length
10
ns