Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet

32099G–06/2011

The maximum SPI slave output frequency is given by the following formula:

Where 

 is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA.

 is

the SPI master setup time. Please refer to the SPI master datasheet for 

.

 is the

maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this
clock.

 is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteris-

tics section for the maximum frequency of the pins.

Figure 7-13. SPI Master Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)

Figure 7-14. SPI Master Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)

2

×

9

-----------------------------

,

1

+

------------------------------------

(

,

)

=

SPI0

SPI1

MISO

SPCK

MOSI

SPI2

SPI3

SPI4

MISO

SPCK

MOSI

SPI5