Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet

32099G–06/2011

Figure 7-18. JTAG Interface Signals

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

JTAG2

JTAG3

JTAG1

JTAG4

JTAG0

TMS/TDI

TCK

TDO

JTAG5

JTAG6

JTAG7

JTAG8

JTAG9

JTAG10

Boundary

Scan Inputs

Boundary

Scan Outputs

JTAG Timings

JTAG0

TCK Low Half-period

V

VDDIO 

from 

3.0V to 3.6V, 

maximum 

external 

capacitor = 

40pF

23.2

ns

JTAG1

TCK High Half-period

8.8

JTAG2

TCK Period

32.0

JTAG3

TDI, TMS Setup before TCK High

3.9

JTAG4

TDI, TMS Hold after TCK High

0.6

JTAG5

TDO Hold Time

4.5

JTAG6

TCK Low to TDO Valid

23.2

JTAG7

Boundary Scan Inputs Setup Time

0

JTAG8

Boundary Scan Inputs Hold Time

5.0

JTAG9

Boundary Scan Outputs Hold Time

8.7

JTAG10

TCK to Boundary Scan Outputs Valid

17.7