Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet
Product codes
AT32UC3L0-XPLD
85
32099G–06/2011
AT32UC3L016/32/64
Before going to sleep modes where RCSYS is stopped, make sure the division factor
between CPU/HSB and PBx frequencies is less than or equal to 4.
between CPU/HSB and PBx frequencies is less than or equal to 4.
External reset in Shutdown mode
If an external reset is asserted while the device is in Shutdown mode, the Power Manager
will register this as a Power-on reset (POR), and not as a SLEEP reset, in the Reset Cause
register (RCAUSE)
Fix/Workaround
None.
If an external reset is asserted while the device is in Shutdown mode, the Power Manager
will register this as a Power-on reset (POR), and not as a SLEEP reset, in the Reset Cause
register (RCAUSE)
Fix/Workaround
None.
Disabling POR33 may generate spurious resets
Depending on operating conditions, POR33 may generate a spurious reset in one of the fol-
lowing cases:
- When POR33 is disabled from the user interface
- When SM33 supply monitor is enabled
- When entering Shutdown mode while debugging the chip using JTAG or aWire interface
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective
Fix/Workaround
- Do not disable POR33 using the user interface
- Do not use the SM33 supply monitor
- Do not enter Shutdown mode if a debugger is connected to the chip
Depending on operating conditions, POR33 may generate a spurious reset in one of the fol-
lowing cases:
- When POR33 is disabled from the user interface
- When SM33 supply monitor is enabled
- When entering Shutdown mode while debugging the chip using JTAG or aWire interface
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective
Fix/Workaround
- Do not disable POR33 using the user interface
- Do not use the SM33 supply monitor
- Do not enter Shutdown mode if a debugger is connected to the chip
Instability when exiting sleep walking
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
- The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
- A sleep mode where the OSC0 is automatically disabled is entered
- The device enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleepwalking is expected to be used.
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
- The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
- A sleep mode where the OSC0 is automatically disabled is entered
- The device enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleepwalking is expected to be used.
Clock Failure Detector (CFD) can be issued while turning off the CFD
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
Sleepwalking in idle and frozen sleep mode will mask all other PB clocks
If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.
If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.
10.2.4
SCIF
The FLO lock bit (FLOCR.LOCK) does not work
The FLO lock bit does not work and will always read as zero.
Fix/Workaround
The FLO lock bit does not work and will always read as zero.
Fix/Workaround