Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet

32099G–06/2011

Fix/Workaround
None.

Open Mode is not functional
The Open Mode is not functional.
Fix/Workaround
None.

VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x110.
Fix/Workaround
None.

In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS. 

CONFIG register reads 0x4F
The CONFIG register reads 0x4F instead of 0x43.
Fix/Workaround
None.

If is not possible to mask the request clock requests
If is not possible to mask the request clock requests using PPCR.
Fix/Workaround
None.

Static mode cannot be entered if the WDT is using OSC32
If the WDT is using OSC32 as clock source and the user tries to enter Static mode, the
Deepstop mode will be entered instead.
Fix/Workaround
None.

Clock Failure Detector (CFD) does not work
Clock Failure Detector (CFD) does not work.
Fix/Workaround
None.

WCAUSE register should not be used
The WCAUSE register should not be used.
Fix/Workaround
None.

PB writes via debugger in sleep modes are blocked during sleepwalking
During sleepwalking, PB writes performed by a debugger will be discarded by all PB mod-
ules except the module that is requesting the clock.
Fix/Workaround