Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet

Product codes
AT32UC3L0-XPLD
Page of 110
97
32099G–06/2011
AT32UC3L016/32/64
Fix/Workaround
None.
GCLK5 can not be used as source for the CLK_MSR
The frequency for GCLK5 can not be measured by the FREQM.
Fix/Workaround
None.
10.4.11
GPIO
GPIO interrupt can not be cleared when interrupts are disabled
The GPIO interrupt can not be cleared unless the interrupt is enabled for the pin.
Fix/Workaround
Enable interrupt for the corresponding pin, then clear the interrupt.
VERSION register reads 0x210
The VERSION register reads 0x210 instead of 0x211.
Fix/Workaround
None.
10.4.12
USART
The RTS output does not function correctly in hardware handshaking mode
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low. 
10.4.13
SPI
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS. 
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA. 
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.