Atmel SAM4S-EK2 Atmel ATSAM4S-EK2 ATSAM4S-EK2 Data Sheet
Product codes
ATSAM4S-EK2
Evaluation Kit Hardware
SAM4S-EK2 User Guide
4-25
11176A–ATARM–24-Sep-12
4.5.6
JTAG Debugging Connector J6
This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with
the SAM-ICE or any similar third-party interface.
male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with
the SAM-ICE or any similar third-party interface.
Figure 4-30. JTAG/ICE Connector J6
Table 4-14. JTAG/ICE Connector J6 Signal Descriptions
Pin
Mnemonic
Description
1
VTref. 3.3V power
This is the target reference voltage. It is used to check if the target has power, to
create the logic-level reference for the input comparators and to control the output
logic levels to the target. It is normally fed from Vdd on the target board and must
not have a series resistor.
create the logic-level reference for the input comparators and to control the output
logic levels to the target. It is normally fed from Vdd on the target board and must
not have a series resistor.
2
Vsupply. 3.3V power
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to Vdd or leave open in target system.
equipment. Connect to Vdd or leave open in target system.
3
nTRST TARGET RESET — Active-low
output signal that resets the target
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
4
GND
Common ground.
5
TDI TEST DATA INPUT — Serial data
output line, sampled on the rising edge
of the TCK signal
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
defined state on the target board. Typically connected to TDI on target CPU.
6
GND
Common ground.
7
TMS TEST MODE SELECT
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target’s JTAG state machine, sampled on the rising edge of the TCK signal.
Typically connected to TMS on target CPU. Output signal that sequences the
target’s JTAG state machine, sampled on the rising edge of the TCK signal.
8
GND Common
ground.
9
TCK TEST CLOCK — Output timing
signal, for synchronizing test logic and
control register access
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
defined state on the target board. Typically connected to TCK on target CPU.
10
GND
Common ground.
11
RTCK
Input Return test clock signal from the
target
Some targets must synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
12
GND
Common ground.
13
TDO JTAG TEST DATA OUTPUT —
Serial data output from the target
JTAG data output from target CPU. Typically connected to TDO on target CPU.
14
GND
Common ground.