Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

1007

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

EMAC_NCR

0xF802C000

Read-write

Asserts the loopback signal to the PHY.

Connects 

txd 

to 

rxd

, 

tx_en 

to 

rx_dv

, forces full duplex and drives 

rx_clk 

and 

tx_clk 

with MCK divided by 4. 

rx_clk 

and 

tx_clk 

may glitch as the EMAC is switched into and out of internal loop back. It is important that receive and transmit cir-

cuits have already been disabled when making the switch into and out of internal loop back.

When set, enables the EMAC to receive data. When reset, frame reception stops immediately and the receive FIFO is cleared. 
The receive queue pointer register is unaffected.

When set, enables the Ethernet transmitter to send data. When reset transmission, stops immediately, the transmit FIFO and 
control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descriptor list.

Set to one to enable the management port. When zero, forces MDIO to high impedance state and MDC low.

This bit is write only. Writing a one clears the statistics registers.

This bit is write only. Writing a one increments all the statistics registers by one for test purposes.

Setting this bit to one makes the statistics registers writable for functional test purposes.

If set in half duplex mode, forces collisions on all received frames.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

THALT

TSTART

BP

7

6

5

4

3

2

1

0

WESTAT

INCSTAT

CLRSTAT

MPE

TE

RE

LLB

LB