Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
1056
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
46.14.2 Power-Up Sequence
Figure 46-3. VDDCORE and VDDIO Constraints at Startup
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach
their target values prior to the release of POR.
their target values prior to the release of POR.
z
VDDIOP must be
≥ V
ih
(refer to DC characteristics,
, for more details), (Tres + T1) at the latest, after
VDDCORE has reached
V
th+
.
z
VDDIOM must reach V
OH
(refer to DC characteristics,
, for more details), (Tres +T1 +T2) at the latest,
after VDDCORE has reached
V
th+
z
T
RES
is a POR characteristic
z
T1 = 3 x T
SLCK
z
T2 = 16 x T
SLCK
The T
SLCK
min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz).
z
T
RES
= 30 µs
z
T1 = 66 µs
z
T2 = 352 µs
z
VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled into the ROM code.
As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to ensure a reliable
operation of the device.
operation of the device.
VDD (V)
Core
Su
pply POR O
u
tp
u
t
VDDIOtyp
Vih
Vth+
t
S
LCK
<--- Tre
s
--->
VDDIO > Vih
VDDCORE
VDDIO
< T1 >
VDDCOREtyp
Voh
VDDIO > Voh
<------------ T2----------->