Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
1071
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
46.17.5.2 Timing constraints
Notes: 1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC
rising edge and the signal change. The Max access timing is the time between the EDMC rising edge and the signal
stabilizes.
stabilizes.
illustrates Min and Max accesses for EMAC3.
Figure 46-22.Min and Max access time of EMAC output signals
46.17.5.3 MII Mode
Notes: 1. VDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF
2. See Note
Table 46-43. EMAC Signals Relative to EMDC
Symbol
Parameter
Min (ns)
Max (ns)
EMAC
1
Setup for EMDIO from EMDC rising
10 ns
EMAC
2
Hold for EMDIO from EMDC rising
10 ns
EMAC
3
EMDIO toggling from EMDC rising
0 ns
Table 46-44. EMAC MII Timings
Symbol
Parameter
Min (ns)
Max (ns)
EMAC
4
Setup for ECOL from ETXCK rising
10
EMAC
5
Hold for ECOL from ETXCK rising
10
EMAC
6
Setup for ECRS from ETXCK rising
10
EMAC
7
Hold for ECRS from ETXCK rising
10
EMAC
8
ETXER toggling from ETXCK rising
10
25
EMAC
9
ETXEN toggling from ETXCK rising
10
25
EMAC
10
ETX toggling from ETXCK rising
10
25
EMAC
11
Setup for ERX from ERXCK
10
EMAC
12
Hold for ERX from ERXCK
10
EMAC
13
Setup for ERXER from ERXCK
10
EMAC
14
Hold for ERXER from ERXCK
10
EMAC
15
Setup for ERXDV from ERXCK
10
EMAC
16
Hold for ERXDV from ERXCK
10
EMDC
EMDIO
EMAC
3 max
EMAC
1
EMAC
2
EMAC
4
EMAC
5
EMAC
3 min