Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

163

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

SHDW_MR

0xFFFFFE14

Read/Write 

 

Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake-up 
event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released 
(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.

0 = The RTC Alarm signal has no effect on the Shutdown Controller.

1 = The RTC Alarm signal forces the de-assertion of the SHDN pin.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

RTCWKEN

–

15

14

13

12

11

10

9

8

–

–

–

–

7

6

5

4

3

2

1

0

CPTWK0

–

–

WKMODE0

0

0

None. No detection is performed on the wake-up input

0

1

Low to high level

1

0

High to low level

1

1

Both levels change