Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

181

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral
clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core.

The Power Management Controller provides all the clock signals to the system.

PMC input clocks:

z

UPLLCK : From UTMI PLL

z

PLLACK : From PLLA

z

SLCK: slow clock from external 32 kHz oscillator or internal 32 kHz RC oscillator

z

MAINCK: Main Clock from external 12 MHz oscillator or internal 12 MHz RC Oscillator

PMC output clocks:

z

Processor Clock PCK.

z

Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge. The divider can be 2, 
3 or 4. 

z

Each peripheral embeds its own divider, programmable in the PMC User Interface.

z

133 MHz DDR clock

Note:

DDR clock is not available when Master Clock (MCK) equals Processor Clock (PCK).

z

USB Host EHCI High speed clock (UPLLCK)

z

USB OHCI clocks (UHP48M and UHP12M)

z

Two programmable clock outputs: PCK0 and PCK1

z

SMD clock

This allows software control of five flexible operating modes:

z

Normal Mode, processor and peripherals running at a programmable frequency

z

Idle Mode, processor stopped waiting for an interrupt 

z

Slow Clock Mode, processor and peripherals running at low frequency

z

Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for 
an interrupt

z

Backup Mode, Main Power Supplies off, VDDBU powered by a battery