Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the
PMC_PCKx registers.

PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI PLL
output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2
between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. 

Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR
(System Clock Status Register).

Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.

As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change
is actually performed. 

1.

Enabling the 12 MHz Main Oscillator:

The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be
advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the
CKGR_MOR register.

Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be
set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associ-
ated interrupt to MOSCS has been enabled in the PMC_IER register.

2.

Setting PLLA and divider:

All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR register.

The DIVA field is used to control the divider itself. A value between 0 and 255 can be programmed. Divider output
is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider is
turned off.

The OUTA field is used to select the PLLA output frequency range.

The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 254. If MULA is
set to 0, PLLA will be turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by
(MULA + 1).

The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR register
after CKGR_PLLAR register has been written.

Once the PMC_PLLAR register has been written, the user must wait for the LOCKA bit to be set in the PMC_SR
register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the
associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can
be programmed in a single write operation. If at some stage one of the following parameters, MULA, DIVA is mod-
ified, LOCKA bit will go low to indicate that PLLA is not ready yet. When PLLA is locked, LOCKA will be set again.
The user is constrained to wait for LOCKA bit to be set before using the PLLA output clock.

Code Example: 

write_register(CKGR_PLLAR,0x00040805)

If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input clock
multiplied by 5. Once CKGR_PLLAR has been written, LOCKA bit will be set after eight slow clock cycles.