Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
222
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter
Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and
clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and
clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It
acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters
require that the PIO Controller clock is enabled.
acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters
require that the PIO Controller clock is enabled.
Figure 23-5. Input Glitch Filter Timing
Figure 23-6. Input Debouncing Filter Timing
23.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The
Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable
Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit
in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive
samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available,
regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or
assigned to a peripheral function.
Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable
Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit
in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive
samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available,
regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or
assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Additional Interrupt Modes
Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register). The current state of this selection can
be read through the PIO_AIMMR (Additional Interrupt Modes Mask Register)
Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register). The current state of this selection can
be read through the PIO_AIMMR (Additional Interrupt Modes Mask Register)
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle
1 cycle
1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles
up to 2 cycles
1 cycle
1 cycle
PIO_IFCSR = 0
Divided Slow Clock
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle Tdiv_slclk
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 1.5 cycles Tdiv_slclk
PIO_IFCSR = 1