Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
286
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
25.2.1 Matrix Masters
The Bus Matrix manages 12 masters, which means that each master can perform an access concurrently with others,
depending on whether the slave it accesses is available.
depending on whether the slave it accesses is available.
Each master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing,
all the masters have the same decodings.
all the masters have the same decodings.
25.2.2 Matrix Slaves
The Bus Matrix manages 9 slaves. Each slave has its own arbiter, thus allowing a different arbitration per slave to be
programmed.
programmed.
Table 25-1. List of Bus Matrix Masters
Master 0
ARM926 Instruction
Master 1
ARM926 Data
Master 2&3
DMA Controller 0
Master 4&5
DMA Controller 1
Master 6
UDP HS DMA
Master 7
UHP EHCI DMA
Master 8
UHP OHCI DMA
Master 9
ISI DMA
Master 10
EMAC DMA
Table 25-2. List of Bus Matrix Slaves
Slave 0
Internal SRAM
Slave 1
Internal ROM
Slave 2
Soft Modem (SMD)
Slave 3
USB Device High Speed Dual Port RAM (DPR)
USB Host EHCI registers
USB Host OHCI registers
Slave 4
External Bus Interface
Slave 5
DDR2 port 1
Slave 6
DDR2 port 2
Slave 7
DDR2 port 3
Slave 8
Peripheral Bridge 0
Slave 9
Peripheral Bridge 1