Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
314
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
26.5.4 Implementation Examples
The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer
web site to check current device availability.
web site to check current device availability.
26.5.4.1 2x8-bit DDR2 on EBI
Hardware Configuration
Software Configuration
z
Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Register located in the
bus matrix memory space.
bus matrix memory space.
z
Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency.
The DDR2 initialization sequence is described in the sub-section “DDR2 Device Initialization” of the DDRSDRC section.
In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16-D31 data
bus. NFD0_ON_D16 is to be set to 1.
bus. NFD0_ON_D16 is to be set to 1.