Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
35
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
9.
ARM926EJ-S
™
9.1
Description
The ARM926EJ-S processor is a member of the ARM9
™
family of general-purpose microprocessors. The ARM926EJ-S
implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory
management, high performance, low die size and low power are all important features.
management, high performance, low die size and low power are all important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off
between high performance and high code density. It also supports 8-bit Java instruction set and includes features for
efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next
generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved
DSP performance.
between high performance and high code density. It also supports 8-bit Java instruction set and includes features for
efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next
generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved
DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and
software debug.
software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
z
an ARM9EJ-S
™
integer core
z
a Memory Management Unit (MMU)
z
separate instruction and data AMBA AHB bus interfaces
9.2
Embedded Characteristics
z
ARM9EJ-S
™
Based on ARM
®
Architecture v5TEJ with Jazelle Technology
z
Three Instruction Sets
z
ARM
®
High-performance 32-bit Instruction Set
z
Thumb
®
High Code Density 16-bit Instruction Set
z
Jazelle
®
8-bit Instruction Set
z
5-Stage Pipeline Architecture when Jazelle is not Used
z
Fetch (F)
z
Decode (D)
z
Execute (E)
z
Memory (M)
z
Writeback (W)
z
6-Stage Pipeline when Jazelle is Used
z
Fetch
z
Jazelle/Decode (Two Cycles)
z
Execute
z
Memory
z
Writeback
z
ICache and DCache
z
Virtually-addressed 4-way Set Associative Caches
z
8 Words per Line
z
Critical-word First Cache Refilling
z
Write-though and Write-back Operation for DCache Only
z
Pseudo-random or Round-robin Replacement
z
Cache Lockdown Registers
z
Cache Maintenance