Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
428
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
z
00 = Power-down mode is enabled as soon as the SDRAM device is not selected
z
01 = Power-down mode is enabled 64 clock cycles after completion of the last access
z
10 = Power-down mode is enabled 128 clock cycles after completion of the last access
Figure 30-22.Power-down Entry/Exit, Timeout = 0
30.5.4.3 Deep Power-down Mode
The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal voltage
generators inside the device are stopped and all data is lost.
generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is enabled, the
DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit deep power-down mode, the low-
power bits (LPCB) must be set to “00”, an initialization sequence must be generated by software. See
DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit deep power-down mode, the low-
power bits (LPCB) must be set to “00”, an initialization sequence must be generated by software. See
.
Figure 30-23.Deep Power-down Mode Entry
Entry power down mode
Exit power down mode
SDCLK
A[12:0]
READ
BST
NOP
READ
COMMAND
CKE
0
BA[1:0]
DQS[1:0]
Da
Db
D[15:0]
3
DM[1:0]
NOP READ
BST
NOP
PRCHG
NOP
DEEPOWER
NOP
0
Trp
Enter Deep
Power-down
Mode
Power-down
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
Da
Db
D[15:0]
3
DM[1:0]