Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
479
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
Figure 31-16.DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address
31.4.6 Disabling a Channel Prior to Transfer Completion
Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register,
DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx
register bit.
DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx
register bit.
The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with
the EMPTx bit in the Channel Handler Status Register.
the EMPTx bit in the Channel Handler Status Register.
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, CTRLAx,CTRLBx, DSCRx
DMAC buffer transfer
Writeback of control
information of LLI
Is DMAC in
Row 1 ?
Channel disabled by
hardware
Buffer Transfer Completed
Interrupt generated here
DMAC Chained Buffer Transfer
Completed Interrupt generated here
yes
no