Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
520
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
Figure 32-8. NYET Example with Two Endpoint Banks
32.6.10.3 Data IN
32.6.10.4 Bulk IN or Interrupt IN
Data IN packets are sent by the device during the data or the status stage of a control transfer or during an
(interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or
under the control of the DMA channel.
(interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or
under the control of the DMA channel.
There are three ways for an application to transfer a buffer in several packets over the USB:
z
Packet by packet (see
z
below)
z
below)
32.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)
The application can write one or several banks.
A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the
endpoint.
endpoint.
Algorithm Description for Each Packet:
z
The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write
access to the DPR.
access to the DPR.
z
The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window.
z
The application sets TXRDY flag in the UDPHS_EPTSETSTAx register.
The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can
be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
Algorithm Description to Fill Several Packets:
Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application
overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set
by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.
overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set
by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.
The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This
means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
z
The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait
that at least one bank is free.
that at least one bank is free.
z
The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the
application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS.
application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS.
z
If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the
TXRDY bit in the UDPHS_EPTSETSTAx register.
TXRDY bit in the UDPHS_EPTSETSTAx register.
The application is notified that all banks are free, so that it is possible to write another burst of packets by the
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate.
A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register.
t = 0
t = 125 μs
t = 250 μs
t = 375 μs
t = 500 μs
t = 625 μs
data 0 ACK
data 1 NYET
PING
ACK
data 0 NYET
PING
NACK
PING
ACK
Bank 1
Bank 0
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
E
F
F
E
F
E'
F
E
F
F
E'
F
E
F
E: empty
E': begin to empty
F: full
E': begin to empty
F: full