Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

570

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

Name: UDPHS_EPTSTAx 

[x=0..6] 

(ISOENDPT)

0xF803C11C [0], 0xF803C13C [1], 0xF803C15C [2], 0xF803C17C [3], 0xF803C19C [4], 0xF803C1BC [5], 

0xF803C1DC [6]

Read-only 

Toggle Sequencing:

–

 It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to 

the current bank.

– OUT endpoint:

These bits are set by hardware to indicate the PID data of the current bank:

Notes: 1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).

2. These bits are updated for OUT transfer: 

- 

A new data has been written into the current bank.

- 

The user has just cleared the Received OUT Data bit to switch to the next bank.

3. For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/TXRDY_TRER bit 

to know if the toggle sequencing is correct or not.

4. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx 

(disable endpoint).

This bit is set by hardware when a new too-long packet is received. 

Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow 
Error bit is set.

This bit is updated at the same time as the BYTE_COUNT field.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

31

30

29

28

27

26

25

24

SHRT_PCKT

BYTE_COUNT

23

22

21

20

19

18

17

16

BYTE_COUNT

BUSY_BANK_STA

CURBK

15

14

13

12

11

10

9

8

–

ERR_FLUSH

 

ERR_CRC_NT

R

ERR_FL_ISO

TXRDY_TRER

TX_COMPLT

RXRDY_TXKL

ERR_OVFLW

7

6

5

4

3

2

1

0

TOGGLESQ_STA

–

–

–

–

–

–

0

DATA0

DATA0

1

DATA1

DATA1

2

DATA2

Data2 (only for High Bandwidth Isochronous Endpoint)

3

MDATA

MData (only for High Bandwidth Isochronous Endpoint)