Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
582
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
33.3
Block Diagram
Figure 33-1. Block Diagram
Access to the USB host operational registers is achieved through the AHB bus slave interface. The Open HCI host
controller and Enhanced HCI host controller initialize master DMA transfers through the AHB bus master interface as
follows:
controller and Enhanced HCI host controller initialize master DMA transfers through the AHB bus master interface as
follows:
z
Fetches endpoint descriptors and transfer descriptors
z
Access to endpoint data from system memory
z
Access to the HC communication area
z
Write status and retire transfer descriptor
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the corresponding flag in the
host controller operational registers.
host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream
ports can be determined by the software driver reading the root hub’s operational registers. Device connection is
automatically detected by the USB host port logic.
ports can be determined by the software driver reading the root hub’s operational registers. Device connection is
automatically detected by the USB host port logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not dedicate
pads to external over current protection.
pads to external over current protection.
PORT
S
/M 0
PORT
S
/M 1
U
S
B High-
s
peed
Tr
a
n
s
ceiver
HH
S
DPA
HH
S
DMA
Em
b
edded U
S
B
v2.0 Tr
a
n
s
ceiver
Root H
ub
a
nd
Ho
s
t
S
IE
Li
s
t Proce
ss
or
Block
FIFO 64 x
8
HCI
S
l
a
ve Block
OHCI
Regi
s
ter
s
Root
H
ub
Regi
s
ter
s
AHB
ED & TD
Reg
s
i
s
ter
s
Control
HCI
M
as
ter Block
D
a
t
a
AHB
S
l
a
ve
M
as
ter
HF
S
DPA
HF
S
DMA
HH
S
DPB
HH
S
DMB
HF
S
DPB
HF
S
DMB
AHB
AHB
S
l
a
ve
M
as
ter
HCI
S
l
a
ve Block
EHCI
Regi
s
ter
s
HCI
M
as
ter Block
Li
s
t
Proce
ss
or
P
a
cket
B
u
ffer
FIFO
S
OF
Gener
a
tor
Control
D
a
t
a
U
S
B F
S
Tr
a
n
s
ceiver
HF
S
DPC
HF
S
DMC
PORT
S
/M 2
U
S
B High-
s
peed
Tr
a
n
s
ceiver