Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

Product codes
AT91SAM9G25-EK
Page of 1102
587
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
34.
High Speed MultiMedia Card Interface (HSMCI)
34.1
 Description
The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD
Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic
that automatically handle the transmission of commands and, when required, the reception of the associated responses
and data with a limited processor overhead. 
The HSMCI supports stream, block and multi block data read and write, and is compatible with the DMA Controller
(DMAC), minimizing processor intervention for large buffer transfers.
The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may
be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. Only one slot
can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines)
and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one
reserved for future use).
The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences between
SD and High Speed MultiMedia Cards are the initialization process and the bus topology.
HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes dedicated
hardware to issue the command completion signal and capture the host command completion signal disable.
34.2
Embedded Characteristics
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Compatible with MultiMedia Card Specification Version 4.3
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Compatible with SD Memory Card Specification Version 2.0
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Compatible with SDIO Specification Version 2.0
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Compatible with CE-ATA Specification 1.1
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Cards Clock Rate Up to Master Clock Divided by 2
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Boot Operation Mode Support
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High Speed Mode Support
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Embedded Power Management to Slow Down Clock Rate When Not Used
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Supports 1 Multiplexed Slot(s)
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Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card
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Support for Stream, Block and Multi-block Data Read and Write
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Supports Connection to DMA Controller (DMAC)
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Minimizes Processor Intervention for Large Buffer Transfers
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Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access
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Support for CE-ATA Completion Signal Disable Command
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Protection Against Unexpected Modification On-the-Fly of the Configuration Registers