Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed 
thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. The sampling of the BMS 
pin is done at reset.

If BMS is detected at 0, the controller boots on the memory connected to Chip Select 0 of the External Bus Interface.

In this boot mode, the chip starts with its default parameters (all registers in their reset state), including as follows:

z

 The main clock is the on-chip 12 MHz RC oscillator 

z

 The Static Memory Controller is configured with its default parameters

The user software in the external memory performs a complete configuration:

z

Enable the 32768 Hz oscillator if best accuracy is needed

z

Program the PMC (main oscillator enable or bypass mode)

z

Program and Start the PLL

z

Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock

z

Switch the system clock to the new value

If BMS is detected at 1, the boot memory is the embedded ROM and the Boot Program described below is executed. 
(

The ROM Code is a boot program contained in the embedded ROM. It is also called “First level bootloader”.

The ROM Code performs several steps:

z

Basic chip initialization: XTal or external clock frequency detection

z

Attempt to retrieve a valid code from external non-volatile memories (NVM)

z

Execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM

The ROM Code implements the algorithm shown below in 

SAM-BA Monitor

Copy and run it 

in internal SRAM 

Yes

Chip Setup

Valid boot code 

found in one 

NVM

No