Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
641
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
35.
Serial Peripheral Interface (SPI)
35.1
Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data
transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol
opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and
one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data
back to the master at any given time.
transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol
opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and
one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data
back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a
separate slave select signal for each slave (NPCS).
separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
z
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the
slave(s).
slave(s).
z
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There
may be no more than one slave transmitting data during any particular transfer.
may be no more than one slave transmitting data during any particular transfer.
z
Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master
may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.
may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.
z
Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
35.2
Embedded Characteristics
z
Supports Communication with Serial External Devices
z
Master Mode can drive SPCK up to peripheral clock (bounded by maximum bus clock divided by 2)
z
Slave Mode operates on SPCK, asynchronously to Core and Bus ClockFour Chip Selects with External
Decoder Support Allow Communication with Up to 15 Peripherals
Decoder Support Allow Communication with Up to 15 Peripherals
z
Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals
z
Serial Memories, such as DataFlash and 3-wire EEPROMs
z
Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
z
External Coprocessors
z
Master or Slave Serial Peripheral Bus Interface
z
8-bit to 16-bit Programmable Data Length Per Chip Select
z
Programmable Phase and Polarity Per Chip Select
z
Programmable Transfer Delay Between Consecutive Transfers and Delay before SPI Clock per Chip Select
z
Programmable Delay Between Chip Selects
z
Selectable Mode Fault Detection
z
Connection to DMA Channel Capabilities Optimizes Data Transfers
z
One channel for the Receiver, One Channel for the Transmitter