Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data to 0x00, but FRAME remains low.

When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the
Control Register (US_CR) with the bit RSTSTA to 1.

An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one
sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.

D0

D1

D2

D3

D4

D5

D6

D7

TXD

Start 

Bit

Parity

Bit

Stop

Bit

Baud Rate

 Clock

Write

US_CR

TXRDY

TXEMPTY

STPBRK = 1

STTBRK = 1 

Break Transmission

End of Break