Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register. In this case
the SPI lines must be connected as described below:

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The MOSI line drives the input pin RXD

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The MISO line is driven by the output pin TXD

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The SCK line drives the input pin SCK

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The NSS line drives the input pin CTS

In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset). (See 

In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: 

 However, there are some restrictions:

In SPI Master Mode:

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The external clock SCK must not be selected (USCLKS 

≠ 0x3), and the bit CLKO must be set to “1” in the Mode 

Register (US_MR), in order to generate correctly the serial clock on the SCK pin.

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To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior or 
equal to 6.

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If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a 50:50 
mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).

In SPI Slave Mode:

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The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the Mode Register 
(US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the 
signal on the USART SCK pin.

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To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least 
6 times lower than the system clock.