Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

919

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK 
pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on 
the RK pin is:

z

Master Clock divided by 2 if Receiver Frame Synchro is input

z

Master Clock divided by 3 if Receiver Frame Synchro is output

In addition, the maximum clock speed allowed on the TK pin is:

z

Master Clock divided by 6 if Transmit Frame Synchro is input

z

Master Clock divided by 2 if Transmit Frame Synchro is output

A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission.

The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). 

The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). 

To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected 
in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register 
according to the data format selected.

When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When 
the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and 
additional data can be loaded in the holding register.

RK (pin)

Transmitter

Clock

Divider

Clock

CKS

CKO

Data Transfer

CKI

CKG

Receiver
Clock

Clock
Output

MUX

Tri-state

Controller

Tri-state

Controller

INV

MUX