Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
959
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
44.4.4.3 Memory Interface
Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with 16-bit format of
the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter
module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from
the red and blue channels, and two LSBs from the green channel. When grayscale mode is enabled, two memory
formats are supported. One mode supports 2 pixels per word, and the other mode supports 1 pixel per word.
the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter
module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from
the red and blue channels, and two LSBs from the green channel. When grayscale mode is enabled, two memory
formats are supported. One mode supports 2 pixels per word, and the other mode supports 1 pixel per word.
44.4.4.4 FIFO and DMA Features
Both preview and Codec datapaths contain FIFOs. These asynchronous buffers are used to safely transfer formatted
pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a
relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified length burst is
asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of
operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The
destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of
one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address.
The FBD is defined by a series of three words. The first one defines the current frame buffer address (named
DMA_X_ADDR register), the second defines control information (named DMA_X_CTRL register) and the third defines
the next descriptor address (named DMA_X_DSCR). DMA transfer mode with linked list support is available for both
codec and preview datapath. The data to be transferred described by an FBD requires several burst accesses. In the
example below, the use of 2 ping-pong frame buffers is described.
pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a
relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified length burst is
asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of
operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The
destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of
one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address.
The FBD is defined by a series of three words. The first one defines the current frame buffer address (named
DMA_X_ADDR register), the second defines control information (named DMA_X_CTRL register) and the third defines
the next descriptor address (named DMA_X_DSCR). DMA transfer mode with linked list support is available for both
codec and preview datapath. The data to be transferred described by an FBD requires several burst accesses. In the
example below, the use of 2 ping-pong frame buffers is described.
Example
The first FBD, stored at address 0x00030000, defines the location of the first frame buffer. This address is programmed
in the ISI user interface DMA_P_DSCR. To enable Descriptor fetch operation DMA_P_CTRL register must be set to
0x00000001. LLI_0 and LLI_1 are the two descriptors of the Linked list.
in the ISI user interface DMA_P_DSCR. To enable Descriptor fetch operation DMA_P_CTRL register must be set to
0x00000001. LLI_0 and LLI_1 are the two descriptors of the Linked list.
Destination Address: frame buffer ID0 0x02A000 (LLI_0.DMA_P_ADDR)
Transfer 0 Control Information, fetch and writeback: 0x00000003 (LLI_0.DMA_P_CTRL)
Next FBD address: 0x00030010 (LLI_0.DMA_P_DSCR)
Second FBD, stored at address 0x00030010, defines the location of the second frame buffer.
Destination Address: frame buffer ID1 0x0003A000 (LLI_1.DMA_P_ADDR
Transfer 1 Control information fetch and writeback: 0x00000003 (LLI_1.DMA_P_CTRL)
Next FBD address: 0x00030000, wrapping to first FBD (LLI_1.DMA_P_DSCR)
Using this technique, several frame buffers can be configured through the linked list.
frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is
mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored
in a dedicated memory space.
mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored
in a dedicated memory space.
Table 44-8. Grayscale Memory Mapping Configuration for 12-bit Data
GS_MODE
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
0
P_0[11:4]
P_0[3:0], 0000
P_1[11:4]
P_1[3:0], 0000
1
P_0[11:4]
P_0[3:0], 0000
0
0