Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1018
40.2
Embedded Characteristics
4 Channels
Common Clock Generator Providing Thirteen Different Clocks
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A Modulo n Counter Providing Eleven Clocks
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Two Independent Linear Dividers Working on Modulo n Counter Outputs
Independent Channels
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Independent 16-bit Counter for Each Channel
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Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or
Non-Overlapping Time) for Each Channel
Non-Overlapping Time) for Each Channel
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Independent Enable Disable Command for Each Channel
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Independent Clock Selection for Each Channel
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Independent Period, Duty-Cycle and Dead-Time for Each Channel
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Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel
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Independent Programmable Selection of The Output Waveform Polarity for Each Channel, with
Double Buffering
Double Buffering
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Independent Programmable Center- or Left-aligned Output Waveform for Each Channel
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Independent Additional Edge Value for Each Channel, with Double Buffering, in Order to Generate
Additional Edges of the Output Waveform
Additional Edges of the Output Waveform
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Independent Output Override for Each Channel
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Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned
Configuration or at Each Half-Period for Center-Aligned Configuration
Configuration or at Each Half-Period for Center-Aligned Configuration
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Independent Update Time Selection of Double Buffering Registers (Polarity, Duty Cycle and Additional
Edge Value) for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration, at
Each Half-Period for Center-Aligned Configuration
Edge Value) for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration, at
Each Half-Period for Center-Aligned Configuration
2 2-bit Gray Up/Down Channels for Stepper Motor Control
Spread Spectrum Counter to Allow a Constantly Varying Duty Cycle (only for Channel 0)
Synchronous Channel Mode
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Synchronous Channels Share the Same Counter
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Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods
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Synchronous Channels Supports Connection of one Peripheral DMA Controller Channel (PDC or
DMA) Which Offers Buffer Transfer Without Processor Intervention To Update Duty-Cycle Registers
DMA) Which Offers Buffer Transfer Without Processor Intervention To Update Duty-Cycle Registers
2 Independent Events Lines Intended to Synchronize ADC Conversions
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Programmable delay for Events Lines to delay ADC measurements
8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines and PDC or DMA Transfer
Requests
Requests
8 Programmable Fault/Break Inputs Providing an Asynchronous Protection of PWM Outputs
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1 User Driven through PIO Inputs
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PMC Driven when Crystal Oscillator Clock Fails
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ADC Controller Driven through Configurable Comparison Function
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Analog Comparator Controller Driven
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Timer/Counter Driven through Configurable Comparison Function
Register Write Protection