Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
1039
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Figure 40-15. Method 3 (UPDM = 2 and PTRM = 1 and PTRCS = 0)
40.6.2.10 Update Time for Double-Buffering Registers
All channels integrate a double-buffering system in order to
prevent
an unexpected output waveform while
modifying the period, the spread spectrum value, the polarity, the duty-cycle, the additional edge value, the dead-
times, the output override, and the synchronous channels update period.
times, the output override, and the synchronous channels update period.
This double-buffering system comprises the following update registers:
When one of these update registers is written to, the write is stored, but the values are updated only at the next
PWM period border. In left-aligned mode (CALG = 0), the update occurs when the channel counter reaches the
period value CPRD. In center-aligned mode, the update occurs when the channel counter value is decremented
and reaches the 0 value.
PWM period border. In left-aligned mode (CALG = 0), the update occurs when the channel counter reaches the
period value CPRD. In center-aligned mode, the update occurs when the channel counter value is decremented
and reaches the 0 value.
In center-aligned mode, it is possible to trigger the update of the polarity and the duty-cycle the additional edge
value, at the next half period border. This mode concerns the following update registers:
value, at the next half period border. This mode concerns the following update registers:
The update occurs at the first half period following the write of the update register (either when the channel counter
value is incrementing and reaches the period value CPRD, or when the channel counter value is decrementing
and reaches the 0 value). To activate this mode, the user must write a one to the bit UPDS in the
value is incrementing and reaches the period value CPRD, or when the channel counter value is decrementing
and reaches the 0 value). To activate this mode, the user must write a one to the bit UPDS in the
CCNT0
CDTYUPD
0x20
0x40
0x60
UPRCNT
0x0
0x1
0x0
0x1
0x0
0x1
CDTY
UPRUPD
0x1
0x3
CMP0 match
transfer request
WRDY
0x0
0x1
0x2
0x3
0x0
0x1
0x2
UPR
0x1
0x3
0x80
0xA0
0xB0
0x20
0x40
0x60
0x80
0xA0