Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

1046

Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2, an interrupt can be generated at the end of
the corresponding channel period (CHIDx in the PWM Interrupt Status Register 1 (PWM_ISR1)), after a fault event
(FCHIDx in the PWM_ISR1), after a comparison match (CMPMx in the PWM_ISR2), after a comparison update
(CMPUx in the PWM_ISR2) or according to the transfer mode of the synchronous channels (WRDY, ENDTX,
TXBUFE and UNRE in the PWM_ISR2).

If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the
PWM_ISR1 occurs.

If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a
read operation in the PWM_ISR2 occurs.

A channel interrupt is enabled by setting the corresponding bit in PWM_IER1 and PWM_IER2. A channel interrupt
is disabled by setting the corresponding bit in PWM_IDR1 and PWM_IDR2.

To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-
protected by writing the field WPCMD in the 

divided into six groups:



Register group 0:

̶



Register group 1:

̶



Register group 2:

̶

̶

̶

̶

PWM_CMPVUPDx Value

Comparison value

for comparison x

User's Writing

PWM_CMPVx

End of channel0 PWM period and
end of comparison update period

PWM_CMPMUPDx Value

Comparison configuration

for comparison x

PWM_CMPMx

User's Writing

End of channel0 PWM period and
end of comparison update period and
and PWM_CMPMx written