Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
1051
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
40.7.1 PWM Clock Register
Name:
PWM_CLK
Address:
0x40000000
Access:
Read/Write
This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the
.
DIVA, DIVB: CLKA, CLKB Divide Factor
PREA, PREB: CLKA, CLKB Source Clock Selection
31
30
29
28
27
26
25
24
–
–
–
–
PREB
23
22
21
20
19
18
17
16
DIVB
15
14
13
12
11
10
9
8
–
–
–
–
PREA
7
6
5
4
3
2
1
0
DIVA
DIVA, DIVB
CLKA, CLKB
0
CLKA, CLKB clock is turned off
1
CLKA, CLKB clock is clock selected by PREA, PREB
2–255
CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
PREA, PREB
Divider Input Clock
0
0
0
0
Peripheral clock
0
0
0
1
Peripheral clock/2
0
0
1
0
Peripheral clock/4
0
0
1
1
Peripheral clock/8
0
1
0
0
Peripheral clock/16
0
1
0
1
Peripheral clock/32
0
1
1
0
Peripheral clock/64
0
1
1
1
Peripheral clock/128
1
0
0
0
Peripheral clock/256
1
0
0
1
Peripheral clock/512
1
0
1
0
Peripheral clock/1024
Other
Reserved