Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

1194

The 1588 time stamp unit (TSU) is a timer implemented as a 62-bit timer comprising two registers (GMAC_TSL
and GMAC_TN).

The 32 upper bits count seconds and are accessible in the 

 (GMAC_TSL).

The 30 lower bits count nanoseconds and are accessible in the 

 (GMAC_TN). 

The 30 lower bits roll over when they have counted to one second. The timer increments by a programmable
number of nanoseconds with each MCK period and can be adjusted (incremented or decremented) through APB
register accesses.

GMAC is supplied with an AHB DMA interface. When the GMAC is configured to use the DMA, it is attached to the
MAC module’s FIFO to provide a scatter gather type capability for packet data storage in the embedded processor
system or System on Chip.

The GMAC DMA controller performs six types of operation on the AHB bus. When the GMAC DMA is configured in
internal FIFO mode, in order of priority these are as follows:



Receive buffer manager write/read



Transmit buffer manager write/read



Receive data DMA write



Transmit data DMA read

Received frames, optionally including FCS, are written to receive AHB buffers stored in memory. The receive
buffer depth is programmable in the range of 64 bytes to 16 Kbytes through the DMA Configuration Register
(GMAC_DCFGR), with the default being 128 bytes.

The start location for each receive AHB buffer is stored in memory in a list of receive buffer descriptors at an
address location pointed to by the receive buffer queue pointer. The base address for the receive buffer queue
pointer is configured in software using the Receive Buffer Queue Base Address Register (GMAC_RBQB).

Each list entry consists of two words. The first is the address of the receive AHB buffer and the second the receive
status. If the length of a receive frame exceeds the AHB buffer length, the status word for the used buffer is written
with zeroes except for the “start of frame” bit, which is always set for the first buffer in a frame. Bit zero of the
address field is written to 1 to show the buffer has been used. The receive buffer manager then reads the location
of the next receive AHB buffer and fills that with the next part of the received frame data. AHB buffers are filled until
the frame is complete and the final buffer descriptor status word contains the complete frame status. Refer to

 for details of the receive buffer descriptor list.

Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can be offset
by up to three bytes, depending on the value written to bits 14 and 15 of the Network Configuration Register
(GMAC_NCFGR). If the start location of the AHB buffer is offset, the available length of the first AHB buffer is
reduced by the corresponding number of bytes.

31:2

Address of beginning of buffer

1

Wrap—marks last descriptor in receive buffer descriptor list.