Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
1197
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
To function properly, a 10/100 Ethernet system should have no excessive length frames or frames greater than
128 bytes with CRC errors. Collision fragments will be less than 128 bytes long, therefore it will be a rare
occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 bytes for the
receive buffers size.
128 bytes with CRC errors. Collision fragments will be less than 128 bytes long, therefore it will be a rare
occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 bytes for the
receive buffers size.
If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the
receive AHB buffer, then the buffer has been already used and cannot be used again until software has processed
the frame and cleared bit zero. In this case, the “buffer not available” bit in the receive status register is set and an
interrupt triggered. The receive resource error statistics register is also incremented.
receive AHB buffer, then the buffer has been already used and cannot be used again until software has processed
the frame and cleared bit zero. In this case, the “buffer not available” bit in the receive status register is set and an
interrupt triggered. The receive resource error statistics register is also incremented.
43.5.3.2 Transmit AHB Buffers
Frames to transmit are stored in one or more transmit AHB buffers. Transmit frames can be between 1 and 16384
bytes long, so it is possible to transmit frames longer than the maximum length specified in the IEEE 802.3
standard. It should be noted that zero length AHB buffers are allowed and that the maximum number of buffers
permitted for each transmit frame is 128.
bytes long, so it is possible to transmit frames longer than the maximum length specified in the IEEE 802.3
standard. It should be noted that zero length AHB buffers are allowed and that the maximum number of buffers
permitted for each transmit frame is 128.
The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer descriptors at a
location pointed to by the transmit buffer queue pointer. The base address for this queue pointer is set in software
using the Transmit Buffer Queue Base Address Register. Each list entry consists of two words. The first is the byte
address of the transmit buffer and the second containing the transmit control and status. For the FIFO-based DMA
configured with a 32-bit data path the address of the buffer is a byte address.
location pointed to by the transmit buffer queue pointer. The base address for this queue pointer is set in software
using the Transmit Buffer Queue Base Address Register. Each list entry consists of two words. The first is the byte
address of the transmit buffer and the second containing the transmit control and status. For the FIFO-based DMA
configured with a 32-bit data path the address of the buffer is a byte address.
Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad will
also be automatically generated to take frames to a minimum length of 64 bytes. When CRC is not automatically
generated (as defined in word 1 of the transmit buffer descriptor or through the control bus of FIFO), the frame is
assumed to be at least 64 bytes long and pad is not generated.
also be automatically generated to take frames to a minimum length of 64 bytes. When CRC is not automatically
generated (as defined in word 1 of the transmit buffer descriptor or through the control bus of FIFO), the frame is
assumed to be at least 64 bytes long and pad is not generated.
An entry in the transmit buffer descriptor list is described in
To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits [31:0] in
the first word of each descriptor list entry.
the first word of each descriptor list entry.
The second word of the transmit buffer descriptor is initialized with control information that indicates the length of
the frame, whether or not the MAC is to append CRC and whether the buffer is the last buffer in the frame.
the frame, whether or not the MAC is to append CRC and whether the buffer is the last buffer in the frame.
After transmission the status bits are written back to the second word of the first buffer along with the used bit. Bit
31 is the used bit which must be zero when the control word is read if transmission is to take place. It is written to
one once the frame has been transmitted. Bits[29:20] indicate various transmit error conditions. Bit 30 is the wrap
bit which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues to
increment.
31 is the used bit which must be zero when the control word is read if transmission is to take place. It is written to
one once the frame has been transmitted. Bits[29:20] indicate various transmit error conditions. Bit 30 is the wrap
bit which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues to
increment.
The Transmit Buffer Queue Base Address Register can only be updated while transmission is disabled or halted;
otherwise any attempted write will be ignored. When transmission is halted the transmit buffer queue pointer will
maintain its value. Therefore when transmission is restarted the next descriptor read from the queue will be from
immediately after the last successfully transmitted frame. while transmit is disabled (bit 3 of the network control set
low), the transmit buffer queue pointer resets to point to the address indicated by the Transmit Buffer Queue Base
Address Register. Note that disabling receive does not have the same effect on the receive buffer queue pointer.
otherwise any attempted write will be ignored. When transmission is halted the transmit buffer queue pointer will
maintain its value. Therefore when transmission is restarted the next descriptor read from the queue will be from
immediately after the last successfully transmitted frame. while transmit is disabled (bit 3 of the network control set
low), the transmit buffer queue pointer resets to point to the address indicated by the Transmit Buffer Queue Base
Address Register. Note that disabling receive does not have the same effect on the receive buffer queue pointer.
Once the transmit queue is initialized, transmit is activated by writing to the transmit start bit (bit 9) of the Network
Control Register. Transmit is halted when a buffer descriptor with its used bit set is read, a transmit error occurs, or
by writing to the transmit halt bit of the Network Control Register. Transmission is suspended if a pause frame is
received while the pause enable bit is set in the Network Configuration Register. Rewriting the start bit while
transmission is active is allowed. This is implemented with TXGO variable which is readable in the Transmit Status
Register at bit location 3. The TXGO variable is reset when:
Control Register. Transmit is halted when a buffer descriptor with its used bit set is read, a transmit error occurs, or
by writing to the transmit halt bit of the Network Control Register. Transmission is suspended if a pause frame is
received while the pause enable bit is set in the Network Configuration Register. Rewriting the start bit while
transmission is active is allowed. This is implemented with TXGO variable which is readable in the Transmit Status
Register at bit location 3. The TXGO variable is reset when:
Transmit is disabled.
A buffer descriptor with its ownership bit set is read.
Bit 10, THALT, of the Network Control Register is written.